Electrical Engineer Resume Summary Examples

Recent BSEE graduate (May 2025, Magna Cum Laude, GPA 3.8) targeting a junior power-systems engineering role at a US investor-owned utility, ISO, or EPC firm. During an Allen Bradley-sponsored capstone and a six-month internship at a midsize EPC firm, I drafted protection-coordination one-lines for a 138 kV / 24.9 kV substation rebuild, ran short-circuit and arc-flash sweeps in SKM PowerTools and ETAP across 14 buses, and supported the IEEE 1584 incident-energy classification that was used in the contractor work-package. EIT-certified (California, December 2025), targeting PE eligibility in 2029. Comfortable with AutoCAD Electrical, ETAP, SKM PowerTools, basic PSCAD, NEC 2023 article navigation. GitHub project portfolio includes a small SCADA-tag simulator built on open-source IEC 61850 libraries. Looking for a substation-design or protection-engineering track at a firm with a structured PE-mentorship path.

Recent BSEE graduate (May 2025, IIT Bombay, GPA 9.1/10) targeting a junior RTL or design-verification engineering role at a US, Israel, or Taiwan semiconductor team. Capstone shipped a 5-stage pipelined RISC-V core in SystemVerilog with a UVM testbench achieving 94.7% line coverage and 88.2% functional coverage on a 12-suite regression in Synopsys VCS, synthesized to Skywater 130 nm open-PDK using Yosys / OpenROAD with worst-case slack at -42 ps. Comfortable with SystemVerilog, UVM basics, Synopsys VCS, Verdi waveform debug, Git, Linux, basic Python for test bring-up. Two GitHub repos with cleanly documented testbenches and synthesis flows, not unfinished forks. Looking for a junior RTL or DV role at a team taping out at 7 nm or below, with mentorship from a tape-out lead.

Recent BSEE graduate (May 2025, BS, Cum Laude) with internship experience in mixed-signal PCB design for consumer wearables. At a 38-person hearable-audio startup I owned the 6-layer Altium Designer 24 redesign of a charging-cradle PCBA — added a USB-C PD 3.1 sink controller, repositioned the QFN PMIC for thermal margin, and shipped a board that passed FCC Part 15B pre-compliance on first scan in a 3-meter chamber. Comfortable with Altium Designer 24, KiCad 8, LTspice, basic PSpice, hand-soldering 0402 / QFN / BGA-144 for rework, and Saleae logic-analyzer debug. GitHub portfolio: 3 personal PCB projects (USB-C tester, sensor breakout, motor driver) with manufactured boards, not just schematics. Targeting a junior hardware or PCB-design role at a medical-device, EV, or consumer-product team.

Recent BSEE graduate (May 2025, BS in EE with Embedded Systems concentration, GPA 3.7) targeting a junior firmware or embedded-systems engineering role at an automotive, medical-device, or robotics team. Senior project shipped a CAN-bus motor-controller firmware on STM32H7 (Cortex-M7 at 480 MHz) running FreeRTOS — implemented field-oriented-control (FOC) on a 48 V BLDC at 20 kHz PWM, reduced quiescent current from 220 µA to 38 µA in sleep state via peripheral-clock gating, and shipped a JTAG-debuggable build that I bring-up demonstrated at IEEE Region 5 student conference (third-place finish). Comfortable with C / C++ on ARM Cortex-M, FreeRTOS, STM32CubeIDE, Segger Ozone for JTAG/SWD debug, I2C / SPI / UART / CAN peripheral bring-up, and basic Yocto Linux build flow. GitHub portfolio: 4 pinned firmware repos with documented bring-up logs. Looking for a junior embedded role at a team shipping firmware to production, not prototypes-only.

Senior Power Systems Engineer, PE (California, license #E12345 — verifiable on DCA records), with 8 years across utility-scale substation, transmission-interconnection, and grid-modernization work. Led protection-and-control design on six 230 kV / 500 kV interconnection studies for AI-data-center hyperscaler customers (cumulative load 1.84 GW), closed the IEEE 1584 arc-flash and short-circuit studies on three of those projects, and chaired the protection-coordination review board across two regional utility groups. Authored the EPC firm's internal SEL-relay-setting style guide adopted by 14 protection engineers, and led the SCADA-IEC 61850 digital-substation pilot at a 230 kV greenfield site that has since become the firm's reference architecture. Strongest in protection coordination, IEEE 1584 / IEEE C37.230 closure, and the social-engineering side of getting cross-utility working groups aligned on protection settings. Targeting a principal protection engineer or substation-engineering lead role at an investor-owned utility, ISO, or top-tier EPC firm working on HVDC interconnection.

Senior Physical Design Engineer with 7 years across mobile, networking, and AI-accelerator silicon at three taping-out semiconductor teams. Currently own the place-and-route and signoff for the SerDes-adjacent control block on our company's first 2 nm AI accelerator (TSMC N2 node) — drove the floorplan from concept through ECO and post-silicon bring-up; closed Innovus PR with worst-case slack at +12 ps under the timing margin band; signed off STA in PrimeTime across PVT corners; signoff-clean on Calibre DRC and LVS; held leakage power within the 78 mW budget on a 2.1 mm² block running at 1.8 GHz. Lead PD reviewer for a sister 3 nm tape-out; mentored two L3 PD engineers through their first tape-out cycles. Strongest in floorplan-to-signoff PD flow, clock-tree synthesis trade-off (H-tree vs balanced-mesh on tight slack budgets), and the cross-team review discipline of an 18-month tape-out cycle. Comfortable with Cadence Innovus, Synopsys ICC2 (cross-flow), Synopsys PrimeTime, Synopsys StarRC, Cadence Tempus, Siemens Calibre DRC / LVS, Synopsys VCS for unit-level sign-off sims, TCL for flow scripting, and Python for data-extraction tooling. Targeting a staff PD engineer or PD-lead role at an AI-accelerator, GPU, or networking-ASIC team taping out at N2 / A14.

Senior Hardware Engineer with 9 years designing high-power motor-control and traction-inverter boards for EV automotive Tier-1 customers. Most recently led the 12-layer hybrid Cadence Allegro + Ansys SIwave / PowerSI design of an 800 V SiC traction inverter for a European EV OEM platform shipping at 14K units / month — owned the SiC MOSFET gate-driver layout (Wolfspeed XAB450M12XM3 modules), the busbar current-loop minimization that held di/dt-induced overshoot under 5%, and the AEC-Q200 / AEC-Q101 component-qualification trail that survived a 1,200-hour HALT chamber run. Strongest in high-power gate-driver layout, parasitic-loop minimization in SiC / GaN switching power stages, AEC-Q qualification regimes, and the supplier-coordination side of locking down a 130-line BOM through automotive PPAP. Comfortable with Cadence Allegro 17.4, Cadence Sigrity SI / PI, Ansys SIwave / PowerSI, LTspice and PLECS for switching-converter simulation, basic Python for test-fixture automation, and the AEC-Q / ISO 26262 functional-safety documentation regime. Targeting a staff hardware engineer or power-electronics lead role at an EV OEM, traction-inverter Tier-1, or stationary-storage firm building 800 V or higher-voltage systems.

Senior Embedded Linux Engineer with 8 years across robotics, automotive ADAS, and industrial-IoT gateways. Currently own the Yocto / Linux BSP for a 12-axis collaborative-robot controller running on NXP i.MX 8M Plus (Cortex-A53 quad-core, integrated NPU) — built the Yocto layer (`meta-our-robot`) that 14 application engineers consume; brought up the NXP NPU integration for TensorFlow Lite Micro inference on the vision pipeline; closed the EtherCAT real-time motion-control loop with worst-case jitter under 14 µs across a 1 kHz cycle; led the migration from a downstream NXP kernel (`5.10-imx`) to a mainline 6.6 LTS base with the i.MX 8M Plus peripherals tree upstreamed. Strongest in Yocto layer architecture, kernel device-tree work, real-time scheduling (PREEMPT_RT), and the upstream-vs-downstream kernel trade-off vocabulary. Comfortable with Yocto / OpenEmbedded, Buildroot for compare flows, Linux kernel device-tree, PREEMPT_RT, EtherCAT, ROS 2 Humble for higher-layer integration, C / C++, Python, and TensorFlow Lite Micro for the NPU pipeline. Targeting a staff embedded-Linux or BSP-lead role at a robotics, autonomous-systems, or industrial-IoT team running mainline-LTS kernels in production.

Staff Power Systems Engineer, PE (California, Texas, Arizona, Nevada — multi-state) with 14 years across utility-scale substation, HVDC interconnection, and BESS / utility-scale-storage engineering. Most recently led the technical scope on a ±525 kV HVDC link supporting 1.4 GW of offshore wind interconnection (one of the four major HVDC capex projects on the US East Coast in 2026), chaired the cross-company protection-coordination review board across two transmission owners and one ISO, and authored the firm-wide HVDC-converter-station design standard now used on three subsequent bids. Earlier work spanned the protection-engineering scope on twelve 230 kV / 500 kV substation rebuilds, the IEEE 1584 arc-flash methodology paper that the firm submitted to IEEE PES, and the SCADA-IEC 61850 digital-substation reference architecture deployed at six greenfield sites. Strongest in HVDC converter-station engineering, the regulatory and FERC / NERC coordination side of large interconnection projects, and the cross-utility working-group facilitation that consensus-driven engineering requires. Targeting a principal-track power-engineering role at a transmission utility, ISO, or top-tier EPC firm — preferably one with active HVDC and offshore-wind interconnection scope.

Staff RTL Design Engineer with 13 years across mobile-SoC, networking, and AI-accelerator silicon at three taping-out semiconductor teams. Currently the technical lead for the dataflow-fabric subsystem on our company's 2 nm AI training accelerator (TSMC N2 node) — led the architecture-to-RTL freeze cycle for 11 SystemVerilog blocks owned by a 14-engineer subteam, drove the SerDes-adjacent low-latency-control protocol that holds 220 ps end-to-end latency across the on-die fabric, chair the RTL-architecture review board across the broader 84-engineer chip team, and authored the company-wide "RTL coding-style and assertion-discipline" guide now used across three product lines. Previously taped out four chips at N7 / N5 in the networking and storage-controller domains. Strongest in micro-architecture-to-RTL judgment, the verification-vs-RTL trade-off vocabulary at signoff, and the engineer-coaching side of running a 14-engineer subteam through an 18-month tape-out cycle. Comfortable with SystemVerilog, UVM (review-level), Cadence Xcelium, Synopsys VCS, Verdi, Synopsys VC Formal for SV-Assertion-property work, JasperGold (compare flow), TCL flow scripting, Python tooling, and the broader Synopsys-Design-Compiler / Cadence-Genus synthesis flow at the architecture-review level. Targeting a principal RTL or chip-architect role at an AI-accelerator, GPU, or custom-silicon team taping out at N2 / A14.

Staff Hardware Architect with 12 years across consumer-electronics, automotive, and industrial high-power systems at three product organizations of 200-1,200 engineers. Authored the company-wide PCB-stackup and EMC-pre-compliance reference architecture at our current Tier-1 EV traction-inverter business — now governing 14 product platforms across 800 V SiC traction, DC-DC, and onboard-charger product lines. Led the strategic kill of an in-flight 800 V GaN traction-inverter program after the third-party HALT data showed parasitic-induced gate ringing that we could not parasitic-budget out within the program timeline — escalated the decision to the VP of engineering with a 14-page technical write-up; the kill preserved 18 months of budget for the SiC-only roadmap that is now in volume production. Strongest in switching-power-electronics layout architecture, AEC-Q / ISO 26262 functional-safety alignment, and the technical-judgment-plus-political-capital combination that the strategic-kill artifact requires. Targeting a principal-track hardware-architect role at an EV OEM, traction-inverter Tier-1, or hyperscaler-data-center power-distribution-unit (PDU) team.

Staff Embedded Systems Architect with 13 years across automotive ADAS, robotics, and aerospace flight-control firmware at three safety-critical product organizations. Authored the company-wide AUTOSAR-Adaptive architecture and ISO 26262 ASIL-D process artifacts at our current ADAS Tier-1 — now governing the firmware architecture across our forward-camera, surround-view, and central-compute platforms shipping in two German OEM model years. Led the strategic move from a homegrown classic-AUTOSAR-on-AURIX architecture to a hybrid classic + adaptive architecture on a Cortex-A78AE / Cortex-R52 SoC; ran the funding proposal that secured the 18-engineer firmware-architecture-team headcount over four quarters; shipped without a customer-visible regression during a 22-month migration. Strongest in safety-critical systems architecture, AUTOSAR Classic + Adaptive judgment, ISO 26262 ASIL-D process work, and the "fuzzy executive AI-driving priorities into well-scoped firmware-architecture work" translation that staff-track architects spend half their time on. Targeting a principal embedded-architect or chief-firmware-architect role at an ADAS, robotics, or aerospace flight-control team.

Engineering Manager, PE, with 14 years total experience in utility-scale power-systems engineering and 6 years in people-leadership. Currently manage a 22-engineer protection-and-controls team at a major US EPC firm — accountable for the protection-engineering scope across the firm's $1.8B HVDC-and-offshore-wind project portfolio, including the ±525 kV HVDC link supporting 1.4 GW of offshore wind on the US East Coast. Hired 9 engineers in the past 18 months across the structurally tight EE shortage (analog, embedded, and power are the three hardest segments per Quilter 2026); reduced engineering-deliverable rework rate from 14% to 4% on substation P&C scope via the design-review-board cadence that I established; mentored two senior engineers through PE licensure and three through promotion to senior. Strongest in the cross-utility-working-group facilitation, the technical hiring discipline required in a structurally constrained EE market, and the calibration-conversation work of mid-year and end-year promo rounds at engineering scale. PE-licensed (California, Texas), authored the firm's hiring rubric for protection-and-controls engineers adopted firm-wide. Targeting an engineering-director or senior-engineering-manager role at a transmission utility, ISO, or top-tier EPC firm working on HVDC and grid-modernization scope.

Engineering Manager with 15 years in ASIC / SoC design and 7 years in people-leadership at three semiconductor companies. Currently manage a 28-engineer RTL-design-and-verification group at a Bay Area AI-accelerator company — accountable for the RTL freeze and verification sign-off across our 2 nm AI training accelerator (TSMC N2) and its 3 nm successor in early planning. Hired 14 engineers across the structurally tight VLSI hiring market in 18 months (semiconductor / VLSI is among the most-contested 2026 EE segments per the TSMC five-fab 2nm ramp coverage in TechNode); reduced sign-off-blocking-bug count per tape-out from 41 to 14 across two tape-out cycles via the verification-architecture-review-board cadence I established; mentored four engineers through promotion to senior and two through promotion to staff. Strongest in the tape-out-cycle program-management discipline, the cross-team coordination across RTL / DV / PD / DFT / signoff that ASIC tape-outs require, and the calibration-conversation work of running mid-year and end-year promo rounds at 28-engineer scale. Authored the company-wide RTL hiring-rubric and the verification-engineer skills-matrix adopted across three product lines. Targeting an engineering-director or senior-engineering-manager role at an AI-accelerator, GPU, or custom-silicon team taping out at N2 / A14.

Engineering Manager with 16 years in hardware / PCB design and 8 years in people-leadership at three product organizations spanning consumer electronics, medical devices, and EV / industrial high-power systems. Currently manage a 19-engineer hardware-design team at a Tier-1 EV traction-inverter business — accountable for the hardware-design scope across our 800 V SiC traction, DC-DC, and onboard-charger product lines shipping in two German OEM platforms. Hired 6 engineers in 18 months in a market where Quilter's 2026 shortage report cites analog (44%) and embedded (43%) as the two hardest segments to fill; reduced PCB-respin rate per program from 3.2 boards to 1.4 boards across four programs via the design-review-checklist and EMC-pre-compliance discipline I established; mentored three engineers through promotion to senior and one through promotion to staff. Strongest in the technical-hiring discipline required in a structurally constrained hardware market, the cross-team coordination of mechanical / thermal / firmware / EE that high-power EV systems require, and the supplier-coordination escalation work that automotive PPAP cycles demand. Authored the firm's hardware-engineer skills-matrix and the EMC-pre-compliance playbook adopted across two product organizations. Targeting an engineering-director or senior-engineering-manager role at an EV OEM, traction-inverter Tier-1, or hyperscaler-data-center power-distribution-unit (PDU) team.

Engineering Manager with 15 years in safety-critical embedded firmware and 7 years in people-leadership at three product organizations spanning automotive ADAS, robotics, and aerospace flight-control. Currently manage a 24-engineer firmware team at an ADAS Tier-1 — accountable for the firmware scope across our forward-camera, surround-view, and central-compute platforms shipping in two German OEM model years. Hired 11 engineers in 18 months in the structurally tight embedded market (per Quilter 2026, embedded is the #2 hardest segment to fill at 43%); reduced ISO 26262 ASIL-D process-audit findings from 28 to 7 across two model-year cycles via the safety-case-review-board cadence I established; mentored five engineers through promotion to senior and two through promotion to staff. Strongest in the safety-critical engineering-management discipline (ISO 26262 ASIL-D, MISRA-C compliance, formal-tool-chain qualification), the technical-hiring discipline that the analog / embedded shortage requires, and the calibration-conversation work of running cross-OEM promo rounds. Authored the firm's firmware-engineer skills-matrix and the ASIL-D safety-case-review checklist adopted across three platforms. Targeting an engineering-director or senior-engineering-manager role at an ADAS Tier-1, robotics, autonomous-systems, or aerospace flight-control team.